The present invention is directed to a protection circuit and, more particularly, to an on-chip surge protection circuit.
With high demand for the consumer electronic product, especially mobile products, many mobile products such as cell phones or tablets have a high return rate due to damage caused by current surges. One conventional surge protection method is to provide off-chip surge protection for integrated circuits (ICs) by adding off-chip Transient Voltage Suppression (TVS) diodes. However, such TVS diodes require additional space and increase circuit board cost. Thus, it is desired to have an on-chip surge protection circuit. Some on-chip Electro-Static Discharge (ESD) protection methods have been proposed.
FIG. 1 is a schematic block diagram of a conventional rail clamp based, on-chip ESD protection circuit 10. The ESD protection circuit 10 has an ESD immunity capability that meets the requirements defined by JEDEC standards and IEC61000-4-2. The ESD protection circuit 10 includes an AC trigger circuit 12 and an ESD current conducting circuit 14.
FIG. 2 is a schematic circuit diagram of the ESD protection circuit 10 shown in FIG. 1. In the ESD protection circuit shown in FIG. 2, the AC trigger circuit 12 includes a resistor R21, a capacitor C21, a P-type transistor MP21 and a resistor R22, and the ESD current conducting circuit 14 includes a large N-type transistor MN21.
When ESD pulses occur, the AC trigger circuit 12 responds fast enough for these ESD pulses, then triggers the ESD current conducting circuit MN21 to turn on and conduct the ESD currents to ground.
The AC trigger circuit 12 is powered by the ESD pulses, and the ESD currents charge the capacitor C21 to generate Vgs for the P-type transistor MP21. The P-type transistor MP21 and the resistor R21 then turn on the N-type transistor MN21. The N-type transistor MN21 operates in a normal MOSFET mode, not in a bipolar mode, during the ESD events. The N-type transistor MN21 turns on and remains active to conduct the ESD currents to ground.
However, the ESD current conducting circuit 14 can only be active for several hundreds of nanoseconds or less, which is much less than the period of surge events, which are around 50 μs or longer pulse duration. Therefore the conventional ESD protection circuit 10 cannot handle surge events. Thus, some solutions have been proposed to use the off-chip TVS diodes to solve this problem, but using off-chip TVS diodes still does not address the problems of increased board space and cost.
FIG. 3 is a schematic circuit diagram of another conventional on-chip surge protection circuit 20. The surge protection circuit 20 includes a DC trigger circuit and an AC trigger circuit. The DC trigger circuit includes a diode D31 and a resistor R31, and the AC trigger circuit includes a capacitor C31, a resistor R32, a N-type transistor MN32, and the resistor R31. The N-type transistor MN31 is used as an ESD current conducting circuit. The diode D31 is configured between a surge clamp voltage output terminal Vsurge and a gate of the N-type transistor MN31.
During surge events, the diode D31 enters a reverse turn-on state when a surge input voltage exceeds a predetermined voltage, and then currents flow through the resistor R31, thereby generating a bias voltage at the gate of the N-type transistor MN31. When the bias voltage at the gate of the N-type transistor MN31 becomes large enough, the N-type transistor MN31 turns on and clamps the surge input voltage at a relatively low voltage and surge currents are conducted to ground.
Although the circuit shown in FIG. 3 is realized an on-chip surge protection circuit, it has the following problems:
(1) Variation of the clamp output voltage generated by the surge protection circuit is very large along with different levels of surge pulses. Since different levels of surge pulses cause a large voltage variation on the resistor R31, and the voltage variation on the resistor R31 causes a large voltage variation at the gate of the N-type transistor MN31, there is a large variation of the clamp output voltage.
(2) The voltage headroom required by this surge protection circuit is large because the voltage required to turn on the N-type transistor MN31 is added to the clamp output voltage, which causes the clamp output voltage to be possibly above a breakdown voltage of the N-type transistor MN31 or a circuit being protected.
It is desired to have an on-chip surge protection circuit that is capable of solving the above issues, especially to have an on-chip surge protection circuit which has several tens of volt voltages to one hundred volt voltage surge immunity level in mobile applications.